This invention relates to semiconductor devices. In particular, this invention relates to reduction of power consumption of DRAM (Dynamic Random-Access Memory) devices.
In proportion as storage capacity of a DRAM device is increasing, its power consumption is increasing in recent years. Techniques for decreasing power consumption of DRAM devices are being required more strongly. In order to elevate voltage of signals to step-up voltage, DRAM devices include internal electrical power source, or internal power supply circuits, which is inefficient to transform voltage. It is therefore required to reduce power consumption for generating step-up voltage.
According to one technique for reducing the power consumption, an external power supply circuit elevates signal voltage to a first level, which is lower than the predetermined step-up voltage, and then, the internal power supply circuit elevates the signal voltage from the first level to the step-up voltage. Generally, external power supply circuits are more efficient than internal ones. Therefore the power consumption can be reduced.
With reference to FIG. 1, a DRAM 1 to which the above-mentioned technique is adopted is described. In the DRAM 1, each sense amplifier 2 is connected to two plates 3, 4. The left side of the sense amplifier 2 is connected to the plate 3. The right side of the sense amplifier 2 is connected to the plate 4. Signals, or faint differences of voltages, are provided from cells on the plates 3 and 4 to the sense amplifier 2. Namely, the difference of voltage between the signals BLTP0 and BLNP0 is provided from the cell (P0) on the plate 3 to the sense amplifier 2 via bit lines BLTSA and BLNSA. The difference of voltage between the signals BLTP1 and BLNP1 is provided from the cell (P1) on the plate 4 to the sense amplifier 2 via the bit lines BLTSA and BLNSA. The sense amplifier 2 amplifies these differences of voltages. A shared signal TGL is connected between the sense amplifier 2 and the plate 3. Another shared signal TGR is connected between the sense amplifier 2 and plate 4.
Conventionally, the shared signals TGL and TGR are generated by a shared signal generating circuit 10 shown in FIG. 2. The signal TGS is input to inverters 11L and 11R. A plate-selecting signal P0EN is input to an inverter 12R. A plate-selecting signal P1EN is input to an inverter 12L. The outputs from the inverter 11L and 12L are provided to a NAND circuit 13L. The output of the NAND circuit 13L is divided into two lines. One is input via inverters 14L and 15L to a NOR circuit 16L. The other is directly input to the NOR circuit 16L. It is assumed that the inverters 14L and 15L have enough delay time. The inverters 14L, 15L and the NOR circuit 16L cause timing for switching from an external voltage source VDD to a step-up voltage source VPP. A NAND circuit 13R, inverters 14R, 15R and a NOR circuit 16R act in similar fashion. The step-up voltage source VPP is provided via transistors 18L, 19L, 20L, 18R, 19R and 20R. The external voltage source VDD is provided via transistors 21L and 21R.
As shown in FIG. 3, when the shared signal generating circuit 10 pre-charges the cell on the plate 3, first, the shared signal TGR is charged by the external voltage source VDD during the time period t1 and then, the shared signal TGR is charged by the step-up voltage source VPP during the time period t2. Hereinafter, the time period t1 may be referred to as the external charging period, and the time period t2 may b referred to as the internal charging period.
It is noted that the inclination of the signal TGR in FIG. 3 is smaller in the time period t1 than in the time period t2. It is further noted that if the external voltage source VDD charges the shared signal for a longer time period, then the power consumption for charging the shared signal becomes smaller.
In order to meet requirement of cell restore characteristic (tRC specification) of a DRAM device, the external charging period in the sense cycle receives severer restriction than that in the pre-charge cycle. On the other hand, because of the circuitry of the shared signal generating circuit 10, the external charging period in the pre-charge cycle is equal to that in the sense cycle. Therefore, the external charging period in the pre-charge cycle receives the same restriction as that in the sense cycle does. Namely, the circuitry of the circuit 10 shortens the external charging period in the pre-charge cycle, and consequently, causes unnecessary power consumption.
Further, power consumption at the step-up voltage supply circuit generates noise. Therefore, it the internal charging period in the pre-charge cycle is becoming longer, then the amount of the noise generated from the internal voltage source VPP in the pre-charge cycle is becoming larger, and consequently, pre-charge characteristic (tRP specification) is becoming worse.
This invention provides methods and circuits for reducing power consumption for providing the shared signals.
According to one aspect of this invention, a method of charging a signal in a semiconductor memory device is provided. The method is applied to the s miconductor memory device includes first and second voltage sources that have at least one different charging characteristic from each other. The semiconductor memory device performs first and second cycles each of which includes steps of charging the signal by the first voltage source, switching from the first voltage source to the second voltage source, and charging the signal by the second voltage source after the switching step. At least one of a first time period, for which the first voltage source charges the signal, and a second time period, for which the second voltage source charges the signal, in the first cycle is different from that/those in the second cycle.
For example, the charging characteristic is power consumption for charging the signal. Another example of the charging characteristic is charging speed for charging the signal.
For example, the first cycle is the sense cycle of the semiconductor memory device, and the second cycle is the pre-charging cycle of the semiconductor memory device.
Typically, the first time period in the first cycle is shorter than that in the second cycle.
The first voltage source may be an external voltage source of the semiconductor memory device, and the second voltage source may be an internal voltage source of the semiconductor memory device. The second voltage source may be the step-up voltage source.
Furthermore, according to another aspect of this invention, a circuit for charging a signal in a semiconductor memory device is provided. The circuit is installed in the semiconductor memory device includes first and second voltage sources that have at least one different charging characteristic from each other. The semiconductor memory device performs first and second cycles each of which includes steps of charging the signal by the first voltage source, switching from the first voltage source to the second voltage source, and charging the signal by the second voltage source after the switching step. At least one of a first time period, for which the first voltage source charges the signal, and a second time period, for which the second voltage source charges the signal, in the first cycle is different from that/those in the second cycle.
The semiconductor memory device may include sense amplifiers each of which is connected to two cells. In this case, the circuit for example includes a timing circuit for changing the time instance to perform the switching step in response to a selecting signal for selecting one of the two cells.
For example, timing circuit may include at least one capacitor one of whose terminals is connected to the selecting signal. Otherwise, th timing circuit may include a NOR circuit one of whose inputs is connect d to the selecting signal.
Furthermore, according to another aspect of this invention, a semiconductor memory device including the above-mentioned circuit is provided.
This invention extends the external charging period and shortens the internal charging period in the sense cycle, and to the contrary, extends the internal charging period and shortens the external charging period in the pre-charge cycle. Consequently, at the same time, this invention can restrict the whole charging time in the sense cycle and reduce power consumption for providing the shared signal.